测试2

树老大

50kW
150kW 150kW
A
1
A
3
VOUT
VIN-
6
REF
5
RFI Filtered Inputs
2
V+
7
V-
4
1
8
150kW 150kW
50kW
A
2
VIN+ RFI Filtered Inputs
3
INA333
RG
G = 1 +
100kW
RG
RFI Filtered Inputs
RFI Filtered Inputs
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBOS445
INA333
ZHCSAK0C –JULY 2008–REVISED DECEMBER 2015
INA333 微功耗(50μA)、零漂移、轨到轨输出仪表放大器
1
1 特性
1• 低偏移电压：25μV（最大值），G ≥ 100
• 低漂移：0.1μV/°C，G ≥ 100
• 低噪声：50nV/√Hz，G ≥ 100
• 高共模抑制比(CMRR)：100dB（最小值），G ≥
10
• 低输入偏置电流：200pA（最大值）
• 电源范围：1.8V 至5.5V
• 输入电压：(V–) + 0.1V 至(V+) – 0.1V
• 输出电压：(V–) + 0.05V 至(V+) – 0.05V
• 低静态电流：50μA
• 工作温度范围：-40°C 至+125°C
• 已过滤射频干扰(RFI) 的输入
• 8 引脚VSSOP 和8 引脚WSON 封装
2 应用范围
• 桥式放大器
• 心电图(ECG) 放大器
• 压力传感器
• 医疗仪表
• 便携式仪表
• 衡器
• 热电偶放大器
• 电阻式温度检测器(RTD) 传感器放大器
• 数据采集
3 说明
INA333 器件是一款低功耗的精密仪表放大器，具有出
色的精度。该器件采用通用的三运算放大器设计，并且
拥有小巧尺寸和低功耗特性，非常适合各类便携式应
用。
可通过单个外部电阻在1 到1000 范围内设置增益。
INA333 设计为采用符合行业标准的增益公式：G = 1
+ (100kΩ/RG)。
INA333 器件拥有超低的偏移电压（25μV，G ≥
100），出色的偏移电压漂移
（0.1μV/°C，G ≥ 100），以及较高的共模抑制比
（100dB，G ≥ 10）。该器件可由低至1.8V (±0.9V)
的电源供电运行，静态电流仅为50μA，因此非常适合
电池供电类系统。INA333 器件采用自动校准技术在扩
展工业温度范围内保证了出色的精度，同时还提供了向
下扩展至直流的超低噪声密度(50nV/√Hz)。
INA333 器件采用8 引脚VSSOP 和WSON 表面贴装
封装，额定温度范围TA = –40°C 至+125°C。
器件信息(1)
器件型号封装封装尺寸（标称值）
INA333
VSSOP (8) 3.00mm × 3.00mm
WSON (8) 3.00mm x 3.00mm
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
简化电路原理图
2
INA333
ZHCSAK0C –JULY 2008–REVISED DECEMBER 2015 [url]www.ti.com.cn[/url]
Copyright © 2008–2015, Texas Instruments Incorporated
目录
1 特性.......................................................................... 1
2 应用范围................................................................... 1
3 说明.......................................................................... 1
4 修订历史记录........................................................... 2
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information ................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics .............................................. 7
7 Detailed Description ............................................ 13
7.1 Overview ................................................................. 13
7.2 Functional Block Diagram ....................................... 13
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 13
8 Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Application ................................................. 14
9 Power Supply Recommendations...................... 19
10 Layout................................................................... 20
10.1 Layout Guidelines ................................................. 20
10.2 Layout Example .................................................... 20
11 器件和文档支持..................................................... 21
11.1 器件支持................................................................ 21
11.2 文档支持................................................................ 22
11.3 商标....................................................................... 22
11.4 静电放电警告......................................................... 22
11.5 Glossary ................................................................ 23
12 机械、封装和可订购信息....................................... 23
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision B (October 2008) to Revision C Page
• 已添加ESD 额定值表，特性描述部分，器件功能模式，应用和实施部分，电源相关建议部分，布局部分，器件和文
档支持部分以及机械、封装和可订购信息部分........................................................................................................................ 1
RG
VINV
IN+
VR
G
V+
VOUT
REF
1
2
3
4
8
7
6
5
Exposed
Thermal
Die Pad
on
Underside
V
INV
IN+
VR
G
V+
V
OUT
1
2
3
4
8
7
6
5
R
G
REF
3
INA333
[url]www.ti.com.cn[/url] ZHCSAK0C –JULY 2008–REVISED DECEMBER 2015
Copyright © 2008–2015, Texas Instruments Incorporated
5 Pin Configuration and Functions
DGK Package
8-Pin VSSOP
Top View
DRG Package
8-Pin WSON
Top View
Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
REF 5 I Reference input. This pin must be driven by low impedance or connected to ground.
RG 1, 8 — Gain setting pins. For gains greater than 1, place a gain resistor between pins 1 and 8.
V+ 7 — Positive supply
V– 4 — Negative supply
VIN+ 3 I Positive input
VIN– 2 I Negative input
VOUT 6 O Output
4
INA333
ZHCSAK0C –JULY 2008–REVISED DECEMBER 2015 [url]www.ti.com.cn[/url]
Copyright © 2008–2015, Texas Instruments Incorporated
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input pins are diode-clamped to the power-supply rails. Input signals that can swing more than 0.3 V beyond the supply rails should be
current limited to 10 mA or less.
(3) Short-circuit to ground.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Supply voltage 7 V
Analog input voltage(2) (V–) – 0.3 (V+) + 0.3 V
Output short-circuit(3) Continuous
Operating temperature, TA –40 150 °C
Junction temperature, TJ 150 °C
Storage temperature, Tstg –65 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings
VALUE UNIT
V(ESD) Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000 V
Machine model (MM) ±200
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VS Supply voltage 1.8 5.5 V
Specified temperature –40 125 °C
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.4 Thermal Information
THERMAL METRIC(1)
INA333
DGK (VSSOP) DRG (WSON) UNIT
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 169.5 60 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 62.7 60 °C/W
RθJB Junction-to-board thermal resistance 90.3 50 °C/W
ψJT Junction-to-top characterization parameter 7.6 — °C/W
ψJB Junction-to-board characterization parameter 88.7 — °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — 6 °C/W
5
INA333
[url]www.ti.com.cn[/url] ZHCSAK0C –JULY 2008–REVISED DECEMBER 2015
Copyright © 2008–2015, Texas Instruments Incorporated
(1) Total VOS, referred-to-input = (VOSI) + (VOSO / G)
(2) RTI = Referred-to-input
(3) 300-hour life test at 150°C demonstrated randomly distributed variation of approximately 1 μV
(4) Does not include effects of external resistor RG
6.5 Electrical Characteristics
for VS = 1.8 V to 5.5 V at TA = 25°C, RL = 10 kΩ, VREF = VS / 2, and G = 1 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT(1)
VOSI Offset voltage, RTI(2) ±10 ±25/G ±25 ±75/G μV
PSR
vs temperature TA = –40°C to +125°C ±0.1 ±0.5 / G μV/°C
vs power supply 1.8 V ≤ VS ≤ 5.5 V ±1 ±5/G ±5 ±15/G μV/V
Long-term stability See (3)
Turnon time to specified VOSI TA = –40°C to +125°C See Typical Characteristics
Impedance
ZIN Differential 100 || 3 GΩ || pF
ZIN Common-mode 100 || 3 GΩ || pF
VCM Common-mode voltage range VO = 0 V (V–) + 0.1 (V+) – 0.1 V
CMR
Common-mode rejection DC to 60 Hz
G = 1 VCM = (V–) + 0.1 V
to (V+) – 0.1 V 80 90 dB
G = 10 VCM = (V–) + 0.1 V
to (V+) – 0.1 V 100 110 dB
G = 100 VCM = (V–) + 0.1 V
to (V+) – 0.1 V 100 115 dB
G = 1000 VCM = (V–) + 0.1 V
to (V+) – 0.1 V 100 115 dB
INPUT BIAS CURRENT
IB
Input bias current ±70 ±200 pA
vs temperature TA = –40°C to +125°C See Figure 26 pA/°C
IOS
Input offset current ±50 ±200 pA
vs temperature TA = –40°C to +125°C See Figure 28 pA/°C
INPUT VOLTAGE NOISE
eNI Input voltage noise
G = 100, RS = 0 Ω, f = 10 Hz 50 nV/√Hz
G = 100, RS = 0 Ω, f = 100 Hz 50 nV/√Hz
G = 100, RS = 0 Ω, f = 1 kHz 50 nV/√Hz
G = 100, RS = 0 Ω, f = 0.1 Hz to 10 Hz 1 μVPP
iN Input current noise
f = 10 Hz 100 fA/√Hz
f = 0.1 Hz to 10 Hz 2 pAPP
GAIN
G Gain equation 1 + (100 kΩ/RG) V/V
Range of gain 1 1000 V/V
Gain error
VS = 5.5 V, (V–) + 100 mV
≤ VO ≤ (V+) – 100 mV
G = 1 ±0.01% ±0.1%
G = 10 ±0.05% ±0.25%
G = 100 ±0.07% ±0.25%
G = 1000 ±0.25% ±0.5%
Gain vs temperature, G = 1 TA = –40°C to +125°C ±1 ±5 ppm/°C
Gain vs temperature, G > 1(4) TA = –40°C to +125°C ±15 ±50 ppm/°C
Gain nonlinearity VS = 5.5 V, (V–) + 100 mV
≤ VO ≤ (V+) – 100 mV
Gain nonlinearity, G = 1 to 1000 RL = 10 kΩ 10 ppm
OUTPUT
Output voltage swing from rail VS = 5.5 V, RL = 10 kΩ See Figure 29 50 mV
Capacitive load drive 500 pF
ISC Short-circuit current Continuous to common –40, +5 mA
6
INA333
ZHCSAK0C –JULY 2008–REVISED DECEMBER 2015 [url]www.ti.com.cn[/url]
Copyright © 2008–2015, Texas Instruments Incorporated
Electrical Characteristics (continued)
for VS = 1.8 V to 5.5 V at TA = 25°C, RL = 10 kΩ, VREF = VS / 2, and G = 1 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
FREQUENCY RESPONSE
Bandwidth, –3dB
G = 1 150 kHz
G = 10 35 kHz
G = 100 3.5 kHz
G = 1000 350 Hz
SR Slew rate
VS = 5 V, VO = 4-V step, G = 1 0.16 V/μs
VS = 5 V, VO = 4-V step, G = 100 0.05 V/μs
tS Settling time to 0.01%
VSTEP = 4 V, G = 1 50 μs
VSTEP = 4 V, G = 100 400 μs
tS Settling time to 0.001%
VSTEP = 4 V, G = 1 60 μs
VSTEP = 4 V, G = 100 500 μs
Overload recovery 50% overdrive 75 μs
REFERENCE INPUT
RIN 300 kΩ
Voltage range V– V+ V
POWER SUPPLY
Voltage range
Single voltage range +1.8 +5.5 V
Dual voltage range ±0.9 ±2.75 V
IQ
Quiescent current VIN = VS / 2 50 75 μA
vs temperature TA = –40°C to +125°C 80 μA
TEMPERATURE RANGE
Specified temperature range –40 125 °C
Operating temperature range –40 150 °C
0
5
10
15
20
25
-
-
-
-
-
0 0.5 1.0 1.5
V (V) CM
V ( V)m OS
2.0 5.0
V = 5V S
2.5 3.0 3.5 4.0 4.5
V = 1.8V S
Time (1s/div)
Gain = 1
Noise (1 V/div)m
-75.0
Output Offset Voltage (mV)
Population
V = 5.5V S
-7.5
0
7.5
15.0
22.5
30.0
37.5
45.0
52.5
60.0
67.5
-15.0
-22.5
-30.0
-37.5
-45.0
-52.5
-60.0
-67.5
75.0
-0.50
Output Voltage Offset Drift (mV/°C)
Population
0.50
V = 5.5V S
-0.05
0
0.05
0.10.15
0.20.25
0.30.35
0.40.45
-0.10
-0.15
-0.20
- 50.2
-0.30
-0.35
-0.40
-0.45
-25.0
Input Offset Voltage (mV)
Population
V = 5.5V S
-2.5
0
2.5
5.0
7.5
10.0
12.5
15.0
17.5
20.0
22.5
-5.0
-7.5
-10.0
-12.5
-15.0
-17.5
-20.0
-22.5
25.0
-0.10
Input Voltage Offset Drift (mV/°C)
Population
0.10
V = 5.5V S
-0.01
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
- 20.0
- 30.0
- 40.0
- 50.0
- 60.0
- 70.0
- 80.0
- 90.0
7
INA333
[url]www.ti.com.cn[/url] ZHCSAK0C –JULY 2008–REVISED DECEMBER 2015
Copyright © 2008–2015, Texas Instruments Incorporated
6.6 Typical Characteristics
at TA = 25°C, VS = 5 V, RL = 10 kΩ, VREF = midsupply, and G = 1 (unless otherwise noted)
Figure 1. Input Offset Voltage Figure 2. Input Voltage Offset Drift (–40°C to 125°C)
Figure 3. Output Offset Voltage Figure 4. Output Voltage Offset Drift (–40°C to 125°C)
Figure 5. Offset Voltage vs Common-Mode Voltage Figure 6. 0.1-Hz to 10-Hz Noise
Time (100ms/div)
Gain = 100
Output Voltage (1V/div)
Time (10ms/div)
Gain = 1
Output Voltage (50mV/div)
0.012
0.008
0.004
0
0.004
0.008
0.012
-
-
-
0 1.0
V (V) OUT
DC Output Nonlinearity Error (%FSR)
0.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
G = 1000
G = 100
G = 10
G = 1
V = ±2.75V S
Time (25ms/div)
Gain = 1
Output Voltage (1V/div)
1000
100
10
1
0.1 1 10 100 1k
Frequency (Hz)
Voltage Noise Density (nV/ ) ÖHz
10k
Current Noise
Output Noise
Input Noise
Total Input-Referred Noise = (Input Noise) +
2 (Output Noise)
G
2
1000
100
10
1
Current Noise Density (f ) A/ÖHz
Time (1s/div)
Gain = 100
Noise (0.5 V/div)m
8
INA333
ZHCSAK0C –JULY 2008–REVISED DECEMBER 2015 [url]www.ti.com.cn[/url]
Copyright © 2008–2015, Texas Instruments Incorporated
Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, RL = 10 kΩ, VREF = midsupply, and G = 1 (unless otherwise noted)
Figure 7. 0.1-Hz to 10-Hz Noise Figure 8. Spectral Noise Density
Figure 9. Nonlinearity Error Figure 10. Large Signal Response
Figure 11. Large-Signal Step Response Figure 12. Small-Signal Step Response
-100
CMRR (mV/V)
Population
100
V = 5.5V S
-10
0
10
20
30
40
50
60
70
80
90
-20
-30
-40
-50
-60
-70
-80
-90
10
8
6
4
2
0
2
4
6
8
10
-
-
-
-
-
-50 -25 0 25 50 75 100
Temperature (°C)
CMRR ( V/V)m
G = 100,
G = 1000
150
V = 2.75V S ±
V = ±0.9V S
125
G = 1
G = 10
80
60
40
20
0
20
40
60
-
-
-
10 100 1k 10k
Frequency (Hz)
Gain (dB)
1M
G = 1
G = 1000
G = 100
G = 10
Time (50ms/div) 100k
Gain = 1
Supply (1V/div)
Supply
VOUT
V (50 V/div)m OUT
10000
1000
100
10
1 10 100
Gain (V/V)
Time ( s)m
1000
0.01%
0.001%
0.1%
Time (100ms/div)
Gain = 100
Output Voltage (50mV/div)
9
INA333
[url]www.ti.com.cn[/url] ZHCSAK0C –JULY 2008–REVISED DECEMBER 2015
Copyright © 2008–2015, Texas Instruments Incorporated
Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, RL = 10 kΩ, VREF = midsupply, and G = 1 (unless otherwise noted)
Figure 13. Small-Signal Step Response Figure 14. Settling Time vs Gain
Figure 15. Start-Up Settling Time Figure 16. Gain vs Frequency
Figure 17. Common-Mode Rejection Ratio Figure 18. Common-Mode Rejection Ratio vs Temperature
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
Output Voltage (V)
Common-Mode Voltage (V)
0 0.2 0.4 0.5 0.8 1.0 1.2 1.4 1.6 1.8
All Gains
V = +1.8V S
V = 0 REF
160
140
120
100
80
60
40
20
0
10 100 1k 10k 100k
Frequency (Hz)
+PSRR (dB)
1 1M
G = 100
G = 1000
G = 10
G = 1
5
4
3
2
1
0
0 1 2 3 4
Output Voltage (V)
Common-Mode Voltage (V)
5
V = +5V S
V = 0 REF
All Gains
0.9
0.7
0.5
0.3
0.1
0.1
0.3
0.5
0.7
0.9
-
-
-
-
-
-0.9 -0.7 -0.5 -0.3 -0.1 0.1
Output Voltage (V)
Common-Mode Voltage (V)
0.9
V = 0.9V S ±
V = 0 REF
0.3 0.5 0.7
All Gains
160
140
120
100
80
60
40
20
0
10 100 1k 10k
Frequency (Hz)
CMRR (dB)
100k
G = 1
G = 1000
G = 100
G = 10
2.5
-2.5 -2.0 -1.0 0 1.0 2.0
Output Voltage (V)
Common-Mode Voltage (V)
2.5
2.0
1.0
0
-1.0
-2.0
2.5
V = 2.5V
V = 0
± S
REF
All Gains
10
INA333
ZHCSAK0C –JULY 2008–REVISED DECEMBER 2015 [url]www.ti.com.cn[/url]
Copyright © 2008–2015, Texas Instruments Incorporated
Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, RL = 10 kΩ, VREF = midsupply, and G = 1 (unless otherwise noted)
Figure 19. Common-Mode Rejection Ratio vs Frequency Figure 20. Typical Common-Mode Range vs Output Voltage
Figure 21. Typical Common-Mode Range vs Output Voltage Figure 22. Typical Common-Mode Range vs Output Voltage
Figure 23. Typical Common-Mode Range vs Output Voltage Figure 24. Positive Power-Supply Rejection Ratio
(V+)
(V+) - 0.25
(V+) - 0.50
(V+) - 0.75
(V+) - 1.00
(V+) - 1.25
(V-) + 1.75
(V-) + 0.75
(V-) + 1.00
(V-) + 0.50
(V-) + 0.25
(V-)
0 10 30 40 50 60
I (mA) OUT
V (V) OUT
(V+) - 1.75
(V+) - 1.50
(V-) + 1.50
(V-) + 1.25
20
+125°C
+25°C
-40°C
VS = ±2.75V
VS = ±0.9V
80
70
60
50
40
30
20
10
0
-50 -25 0 25 50 75 100
Temperature (°C)
I ( A)m Q
125 150
V = 5V S
V = 1.8V S
200
180
160
140
120
100
80
60
40
20
0
0 0.5 1.0 1.5
VCM (V)
| I (pA) B |
2.0 5.0
VS = 5V
2.5 3.0 3.5 4.0 4.5
VS = 1.8V
250
200
150
100
50
0
50
100
-
-
-50 -25 0 25 50 75 100
Temperature (°C)
I (pA) OS
125 150
V = ±0.9V
S
V = ±2.75V
S
160
140
120
100
80
60
40
20
0
-20
0.1 1 10 100 1k 10k 100k
Frequency (Hz)
-PSRR (dB)
1M
G = 1000
V = 5V S
G = 100
G = 1
G = 10
1200
1000
800
600
400
200
0
-200
-50 -25 0 25 50 75 100
Temperature (°C)
I (pA) B
150
+IB
-IB
125
V = ±0.9V
S V = ±2.75V
S
11
INA333
[url]www.ti.com.cn[/url] ZHCSAK0C –JULY 2008–REVISED DECEMBER 2015
Copyright © 2008–2015, Texas Instruments Incorporated
Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, RL = 10 kΩ, VREF = midsupply, and G = 1 (unless otherwise noted)
Figure 25. Negative Power-Supply Rejection Ratio Figure 26. Input Bias Current vs Temperature
Figure 27. Input Bias Current vs Common-Mode Voltage Figure 28. Input Offset Current vs Temperature
Figure 29. Output Voltage Swing vs Output Current Figure 30. Quiescent Current vs Temperature
80
70
60
50
40
30
20
10
0
0 1.0
V (V) CM
I ( A)m Q
2.0 5.0
V = 5V S
3.0 4.0
V = 1.8V S
12
INA333
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Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, RL = 10 kΩ, VREF = midsupply, and G = 1 (unless otherwise noted)
Figure 31. Quiescent Current vs Common-Mode Voltage
50kW
150kW 150kW
A
1
A
3
VOUT
VIN-
6
REF
5
RFI Filtered Inputs
2
V+
7
V-
4
1
8
150kW 150kW
50kW
A
2
VIN+ RFI Filtered Inputs
3
INA333
RG
G = 1 +
100kW
RG
RFI Filtered Inputs
RFI Filtered Inputs
13
INA333
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7 Detailed Description
7.1 Overview
The INA333 is a monolithic instrumentation amplifier (INA) based on the precision zero-drift OPA333 (operational
amplifier) core. The INA333 also integrates laser-trimmed resistors to ensure excellent common-mode rejection
and low gain error. The combination of the zero-drift amplifier core and the precision resistors allows this device
to achieve outstanding DC precision and makes the INA333 ideal for many 3.3-V and 5-V industrial applications.
7.2 Functional Block Diagram
7.3 Feature Description
The INA333 is a low-power, zero-drift instrumentation amplifier offering excellent accuracy. The versatile threeoperational-
amplifier design and small size make the amplifiers ideal for a wide range of applications. Zero-drift
chopper circuitry provides excellent DC specifications. A single external resistor sets any gain from 1 to 10,000.
The INA333 is laser trimmed for very high common-mode rejection (100 dB at G ≥ 100). This devices operate
with power supplies as low as 1.8 V, and quiescent current of 50 μA, typically.
7.4 Device Functional Modes
7.4.1 Internal Offset Correction
INA333 internal operational amplifiers use an auto-calibration technique with a time-continuous 350-kHz
operational amplifier in the signal path. The amplifier is zero-corrected every 8 μs using a proprietary technique.
Upon power up, the amplifier requires approximately 100 μs to achieve specified VOS accuracy. This design has
no aliasing or flicker noise.
7.4.2 Input Common-Mode Range
The linear input voltage range of the input circuitry of the INA333 is from approximately 0.1 V below the positive
supply voltage to 0.1 V above the negative supply. As a differential input voltage causes the output voltage to
increase, however, the linear input range is limited by the output voltage swing of amplifiers A1 and A2. Thus, the
linear common-mode input range is related to the output voltage of the complete amplifier. This behavior also
depends on supply voltage—see Figure 20.
Input overload conditions can produce an output voltage that appears normal. For example, if an input overload
condition drives both input amplifiers to the respective positive output swing limit, the difference voltage
measured by the output amplifier is near zero. The output of the INA333 is near 0 V even though both inputs are
overloaded.
A
1
A
2
A
3
6
150kW 150kW
150kW 150kW
7
4
3
8
1
2
VIN-
VIN+
RG
V+
V-
INA333
G = 1 +
100kW
RG
5
RFI Filter
50kW
50kW
RFI Filter
Load
V = G ´ (V - V ) O IN+ IN-
0.1mF
0.1mF
+
-
VO
RG
Also drawn in simplified form:
INA333
Ref
VO
VIN-
VIN+
Ref
RFI Filter
RFI Filter
14
INA333
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Copyright © 2008–2015, Texas Instruments Incorporated
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The INA333 measures small differential voltage with high common-mode voltage developed between the
noninverting and inverting input. The high input impedance makes the INA333 suitable for a wide range of
applications. The ability to set the reference pin to adjust the functionality of the output signal offers additional
flexibility that is practical for multiple configurations.
8.2 Typical Application
Figure 32 shows the basic connections required for operation of the INA333 device. Good layout practice
mandates the use of bypass capacitors placed close to the device pins as shown.
The output of the INA333 device is referred to the output reference (REF) pin, which is normally grounded. This
connection must be low-impedance to assure good common-mode rejection. Although 15 Ω or less of stray
resistance can be tolerated while maintaining specified CMRR, small stray resistances of tens of Ωs in series
with the REF pin can cause noticeable degradation in CMRR.
Figure 32. Basic Connections
15
INA333
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Typical Application (continued)
8.2.1 Design Requirements
The device can be configured to monitor the input differential voltage when the gain of the input signal is set by
the external resistor RG. The output signal references to the Ref pin. The most common application is where the
output is referenced to ground when no input signal is present by connecting the Ref pin to ground. When the
input signal increases, the output voltage at the OUT pin increases, too.
8.2.2 Detailed Design Procedure
8.2.2.1 Setting the Gain
Gain of the INA333 device is set by a single external resistor, RG, connected between pins 1 and 8. The value of
RG is selected according to Equation 1:
G = 1 + (100 kΩ / RG) (1)
Table 1 lists several commonly-used gains and resistor values. The 100 kΩ in Equation 1 comes from the sum of
the two internal feedback resistors of A1 and A2. These on-chip resistors are laser trimmed to accurate absolute
values. The accuracy and temperature coefficient of these resistors are included in the gain accuracy and drift
specifications of the INA333 device.
The stability and temperature drift of the external gain setting resistor, RG, also affects gain. The contribution of
RG to gain accuracy and drift can be directly inferred from the gain Equation 1. Low resistor values required for
high gain can make wiring resistance important. Sockets add to the wiring resistance and contribute additional
gain error (possibly an unstable gain error) in gains of approximately 100 or greater. To ensure stability, avoid
parasitic capacitance of more than a few picofarads at the RG connections. Careful matching of any parasitics on
both RG pins maintains optimal CMRR over frequency.
(1) NC denotes no connection. When using the SPICE model, the simulation will not converge unless a
resistor is connected to the RG pins; use a very large resistor value.
Table 1. Commonly-Used Gains and Resistor Values
DESIRED GAIN RG (Ω) NEAREST 1% RG (Ω)
1 NC(1) NC
2 100k 100k
5 25k 24.9k
10 11.1k 11k
20 5.26k 5.23k
50 2.04k 2.05
100 1.01k 1k
200 502.5 499
500 200.4 200
1000 100.1 100
8.2.2.2 Internal Offset Correction
The INA333 device internal operational amplifiers use an auto-calibration technique with a time-continuous 350-
kHz operational amplifier in the signal path. The amplifier is zero-corrected every 8 μs using a proprietary
technique. Upon power-up, the amplifier requires approximately 100 μs to achieve specified VOS accuracy. This
design has no aliasing or flicker noise.
8.2.2.3 Offset Trimming
Most applications require no external offset adjustment; however, if necessary, adjustments can be made by
applying a voltage to the REF pin. Figure 33 shows an optional circuit for trimming the output offset voltage. The
voltage applied to REF pin is summed at the output. The operational amplifier buffer provides low impedance at
the REF pin to preserve good common-mode rejection.
10kW
OPA333
±10mV
Adjustment Range
100W
100W
100mA
1/2 REF200
100mA
1/2 REF200
V+
V-
RG INA333
Ref
VO
VIN-
VIN+
16
INA333
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Copyright © 2008–2015, Texas Instruments Incorporated
Figure 33. Optional Trimming of Output Offset Voltage
8.2.2.4 Noise Performance
The auto-calibration technique used by the INA333 device results in reduced low frequency noise, typically only
50 nV/√Hz, (G = 100). The spectral noise density can be seen in detail in Figure 8. Low frequency noise of the
INA333 device is approximately 1 μVPP measured from 0.1 Hz to 10 Hz, (G = 100).
8.2.2.5 Input Bias Current Return Path
The input impedance of the INA333 device is extremely high—approximately 100 GΩ. However, a path must be
provided for the input bias current of both inputs. This input bias current is typically ±70 pA. High input
impedance means that this input bias current changes very little with varying input voltage.
Input circuitry must provide a path for this input bias current for proper operation. Figure 34 shows various
provisions for an input bias current path. Without a bias current path, the inputs float to a potential that exceeds
the common-mode range of the INA333 device, and the input amplifiers will saturate. If the differential source
resistance is low, the bias current return path can be connected to one input (see the thermocouple example in
Figure 34). With higher source impedance, using two equal resistors provides a balanced input with possible
advantages of lower input offset voltage as a result of bias current and better high-frequency common-mode
rejection.
INA333
47kW 47kW
INA333
10kW
Microphone,
Hydrophone,
etc.
Thermocouple
INA333
Center tap provides
bias current return.
17
INA333
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Figure 34. Providing an Input Common-Mode Current Path
8.2.2.6 Input Common-Mode Range
The linear input voltage range of the input circuitry of the INA333 device is from approximately 0.1 V below the
positive supply voltage to 0.1 V above the negative supply. As a differential input voltage causes the output
voltage to increase, however, the linear input range is limited by the output voltage swing of amplifiers A1 and A2.
Thus, the linear common-mode input range is related to the output voltage of the complete amplifier. This
behavior also depends on supply voltage—see Figure 20 to Figure 23 in the Typical Characteristics section.
Input overload conditions can produce an output voltage that appears normal. For example, if an input overload
condition drives both input amplifiers to the respective positive output swing limit, the difference voltage
measured by the output amplifier is near zero. The output of the INA333 is near 0 V even though both inputs are
overloaded.
8.2.2.7 Operating Voltage
The INA333 operates over a power-supply range of 1.8 V to 5.5 V (±0.9 V to ±2.75 V). Supply voltages higher
than 7 V (absolute maximum) can permanently damage the device. Parameters that vary over supply voltage or
temperature are shown in the Typical Characteristics section of this data sheet.
8.2.2.8 Low Voltage Operation
The INA333 device can be operated on power supplies as low as ±0.9 V. Most parameters vary only slightly
throughout this supply voltage range—see the Typical Characteristics section. Operation at very low supply
voltage requires careful attention to assure that the input voltages remain within the linear range. Voltage swing
requirements of internal nodes limit the input common-mode range with low power-supply voltage. Figure 20 to
Figure 23 show the range of linear operation for various supply voltages and gains.
8.2.2.9 Single-Supply Operation
The INA333 device can be used on single power supplies of 1.8 V to 5.5 V. Figure 35 shows a basic singlesupply
circuit. The output REF pin is connected to mid-supply. Zero differential input voltage demands an output
voltage of mid-supply. Actual output voltage swing is limited to approximately 50 mV more than ground, when the
load is referred to ground as shown. Figure 29 shows how the output voltage swing varies with output current.
300W
+3V
150W
R
(1)
1
2V - DV
2V + DV
3V
RG INA333 VO
Ref
1.5V
18
INA333
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Copyright © 2008–2015, Texas Instruments Incorporated
With single-supply operation, VIN+ and VIN– must both be 0.1 V more than ground for linear operation. For
instance, the inverting input cannot be connected to ground to measure a voltage connected to the noninverting
input.
To show the issues affecting low voltage operation, consider the circuit in Figure 35. It shows the INA333 device
operating from a single 3-V supply. A resistor in series with the low side of the bridge assures that the bridge
output voltage is within the common-mode range of the amplifier inputs.
(1) R1 creates proper common-mode voltage, only for low-voltage operation—see Single-Supply Operation.
Figure 35. Single-Supply Bridge Amplifier
8.2.2.10 Input Protection
The input pins of the INA333 device are protected with internal diodes connected to the power-supply rails.
These diodes clamp the applied signal to prevent it from damaging the input circuitry. If the input signal voltage
can exceed the power supplies by more than 0.3 V, the input signal current should be limited to less than 10 mA
to protect the internal clamp diodes. This current limiting can generally be done with a series input resistor. Some
signal sources are inherently current-limited and do not require limiting resistors.
Time (10ms/div)
Gain = 1
Output Voltage (50mV/div)
Time (100ms/div)
Gain = 100
Output Voltage (50mV/div)
Time (25ms/div)
Gain = 1
Output Voltage (1V/div)
Time (100ms/div)
Gain = 100
Output Voltage (1V/div)
19
INA333
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Copyright © 2008–2015, Texas Instruments Incorporated
8.2.3 Application Curves
Figure 36. Large Signal Response Figure 37. Large-Signal Step Response
Figure 38. Small-Signal Step Response Figure 39. Small-Signal Step Response
9 Power Supply Recommendations
The minimum power supply voltage for INA333 is 1.8 V and the maximum power supply voltage is 5.5 V. For
optimum performance, 3.3 V to 5 V is recommended. TI recommends adding a bypass capacitor at the input to
compensate for the layout and power supply source impedance.
RG
V+
VO
Ref
RG
V-IN
V+IN
VVINVIN+
V- GND
Bypass
Capacitor
Gain Resistor
Bypass
Capacitor
GND
V+
VOUT
20
INA333
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版权© 2008–2015, Texas Instruments Incorporated
10 Layout
10.1 Layout Guidelines
Attention to good layout practices is always recommended. Keep traces short and, when possible, use a printedcircuit-
board (PCB) ground plane with surface-mount components placed as close to the device pins as possible.
Place a 0.1-μF bypass capacitor closely across the supply pins. These guidelines should be applied throughout
the analog circuit to improve performance and provide benefits such as reducing the electromagneticinterference
(EMI) susceptibility.
Instrumentation amplifiers vary in the susceptibility to radio-frequency interference (RFI). RFI can generally be
identified as a variation in offset voltage or DC signal levels with changes in the interfering RF signal. The
INA333 device has been specifically designed to minimize susceptibility to RFI by incorporating passive RC
filters with an 8-MHz corner frequency at the VIN+ and VIN– inputs. As a result, the INA333 device demonstrates
remarkably low sensitivity compared to previous generation devices. Strong RF fields may continue to cause
varying offset levels, however, and may require additional shielding.
10.2 Layout Example
Figure 40. INA333 Layout
VCC VCC
Vref+
Vref+
Vref+
Rset 2.5M
VoA2
VoA1
-
+
+
3
1
5
4
2
U5 OPA369
-
+
+
3
1
5
4
2
U6 OPA369
1/2 of matched
monolithic dual
NPN transistors
(example: MMDT3904)
Input I 10n
uC Vref/2 2.5
V
+
VM1
VCC
VCC
Vref+
Vref+
uCVref/2 2.5 V1 5
Vdiff
Vout
+
-
+
U1 OPA335
R3 14k
R8 10k
C1 1n
+
RG
RG V+
V-
Ref
_
Out
2
1
8
3
6
7
5
4 U1 INA333
VCC
1/2 of matched
monolithic dual
NPN transistors
(example: MMDT3904)
NOTE: Temperature compensation
of logging transistors is not shown.
Optional buffer for driving
SAR converters with
sampling systems of ³ 33kHz.
RELATED PRODUCTS
For monolithic logarithmic amplifiers (such as LOG112 or LOG114) see the link in footnote 1.
21
INA333
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版权© 2008–2015, Texas Instruments Incorporated
11 器件和文档支持
11.1 器件支持
11.1.1 开发支持
11.1.1.1 TINA-TI（免费下载软件）
TINA-TI 基于SPICE 的模拟仿真程序（适用于INA333）
TINA 是一款简单、功能强大且易于使用的电路仿真程序，此程序基于SPICE 引擎。TINA-TI 是TINA 软件的一款
免费全功能版本，除了一系列无源和有源模型外，此版本软件还预先载入了一个宏模型库。它提供所有传统的
SPICE 直流(DC)、瞬态和频域分析以及其他设计功能。
TINA-TI 可从Analog eLab Design Center（模拟电子实验室设计中心）免费下载，它提供全面的后续处理能力，
使得用户能够以多种方式形成结果。
虚拟仪器为用户提供选择输入波形和探测电路节点、电压和波形的功能，从而创建一个动态的快速入门工具。
图41 和图42 给出了适用于INA333 器件的TINA-TI 电路示例，这些电路可用于开发、修改和评估特定用途的电
路设计。下面给出了这些仿真文件的下载链接。
注
必须安装TINA 软件（从DesignSoft）或者TINA-TI 软件后才能使用这些文件。请从TINATI
文件夹中下载免费的TINA-TI 软件。
(1) 如下链接会打开TI 对数放大器网页：对数放大器产品主页
图41. 便携式电池供电类系统的低功耗对数函数电路
（例如血糖仪）
要下载包含此电路TINA-TI 仿真文件的压缩文件，请点击如下链接：对数电路。
3V
3V
VREF
3V
VREF
3V
3V
3V
VREF
V4 3
R
2.5k
SET1
W
A
+
IREF1
+
-
+
U3
OPA333
R
2.5k
SET2
W
A
+
IREF2
R
2k
1
W
R
100
ZERO
W
RWb
3W
RWc
4W
RWd
3W
RWa
3W
+
-
+
U2
OPA333
C
470nF
7
OUTF
GNDF
OUTS
GNDS
In
EN
U1 REF3212
+
-
+
OPA3331 OPA333
V
+
VRTD
VT 25
VT+
VT-
Mon+ Mon-
RTD+
RTD-
EMU21 RTD3
R
100k
GAIN
W
VDIFF
T3 BF256A
T1 BF256A
Use BF861A
Use BF861A
G
S
RTD Resistance
(Volts = Ohms)
Temp ( C)
(Volts = C)
°
°
Pt100 RTD
PGA112 MSP430
VREF+
+
RG
V+
V-
Ref
2 _
1
8
3
6
7
5
4 U1 INA333
3V
RG
Out
22
INA333
ZHCSAK0C –JULY 2008–REVISED DECEMBER 2015 [url]www.ti.com.cn[/url]
版权© 2008–2015, Texas Instruments Incorporated
器件支持(接下页)
RWa、RWb、RWc 和RWd 用于仿真线电阻。包含这些电阻是为了展示四线传感技术对线不匹配问题的抗扰性。此方法假定使用四线RTD。
图42. 具有可编程增益采集系统的四线、3V PT100 RTD 调节器
要下载包含此电路TINA-TI 仿真文件的压缩文件，请点击如下链接：PT100 RTD。
11.2 文档支持
11.2.1 相关文档　
相关文档如下：
• 《高精度、低噪声、轨到轨输出、36V、零漂移运算放大器》，SBOS642
• 《50μV VOS、0.25μV/°C、35μA CMOS 运算放大器零漂移系列》，SBOS432
• 《4ppm/°C、100μA、SOT23-6 系列电压基准》，SBVS058
• 《电路板布局布线技巧》，SLOA089
11.3 商标
All trademarks are the property of their respective owners.
11.4 静电放电警告
这些装置包含有限的内置ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止MOS 门极遭受静电损
伤。
23
INA333
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版权© 2008–2015, Texas Instruments Incorporated
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
重要声明
德州仪器(TI) 及其下属子公司有权根据JESD46 最新标准, 对所提供的产品和服务进行更正、修改、增强、改进或其它更改， 并有权根据
JESD48 最新标准中止提供任何产品和服务。客户在下订单前应获取最新的相关信息, 并验证这些信息是否完整且是最新的。所有产品的销售
都遵循在订单确认时所提供的TI 销售条款与条件。
TI 保证其所销售的组件的性能符合产品销售时TI 半导体产品销售条件与条款的适用规范。仅在TI 保证的范围内，且TI 认为有必要时才会使
用测试或其它质量控制技术。除非适用法律做出了硬性规定，否则没有必要对每种组件的所有参数进行测试。
TI 对应用帮助或客户产品设计不承担任何义务。客户应对其使用TI 组件的产品和应用自行负责。为尽量减小与客户产品和应用相关的风险，
客户应提供充分的设计与操作安全措施。
TI 不对任何TI 专利权、版权、屏蔽作品权或其它与使用了TI 组件或服务的组合设备、机器或流程相关的TI 知识产权中授予的直接或隐含权
限作出任何保证或解释。TI 所发布的与第三方产品或服务有关的信息，不能构成从TI 获得使用这些产品或服务的许可、授权、或认可。使用
此类信息可能需要获得第三方的专利权或其它知识产权方面的许可，或是TI 的专利权或其它知识产权方面的许可。
对于TI 的产品手册或数据表中TI 信息的重要部分，仅在没有对内容进行任何篡改且带有相关授权、条件、限制和声明的情况下才允许进行
复制。TI 对此类篡改过的文件不承担任何责任或义务。复制第三方的信息可能需要服从额外的限制条件。
在转售TI 组件或服务时，如果对该组件或服务参数的陈述与TI 标明的参数相比存在差异或虚假成分，则会失去相关TI 组件或服务的所有明
示或暗示授权，且这是不正当的、欺诈性商业行为。TI 对任何此类虚假陈述均不承担任何责任或义务。
客户认可并同意，尽管任何应用相关信息或支持仍可能由TI 提供，但他们将独力负责满足与其产品及在其应用中使用TI 产品相关的所有法
律、法规和安全相关要求。客户声明并同意，他们具备制定与实施安全措施所需的全部专业技术和知识，可预见故障的危险后果、监测故障
及其后果、降低有可能造成人身伤害的故障的发生机率并采取适当的补救措施。客户将全额赔偿因在此类安全关键应用中使用任何TI 组件而
对TI 及其代理造成的任何损失。
在某些场合中，为了推进安全相关应用有可能对TI 组件进行特别的促销。TI 的目标是利用此类组件帮助客户设计和创立其特有的可满足适用
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TI 组件未获得用于FDA Class III（或类似的生命攸关医疗设备）的授权许可，除非各方授权官员已经达成了专门管控此类使用的特别协议。
只有那些TI 特别注明属于军用等级或“增强型塑料”的TI 组件才是设计或专门用于军事/航空应用或环境的。购买者认可并同意，对并非指定面
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TI 已明确指定符合ISO/TS16949 要求的产品，这些产品主要用于汽车。在任何情况下，因使用非指定产品而无法达到ISO/TS16949 要
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IMPORTANT NOTICE
邮寄地址： 上海市浦东新区世纪大道1568 号，中建大厦32 楼邮政编码： 200122
Copyright © 2016, 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
[url]www.ti.com[/url] 12-Aug-2017
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
INA333AIDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-2-260C-1 YEAR -40 to 125 I333
INA333AIDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br)
CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 I333
INA333AIDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-2-260C-1 YEAR -40 to 125 I333
INA333AIDGKTG4 ACTIVE VSSOP DGK 8 250 Green (RoHS
& no Sb/Br)
CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 I333
INA333AIDRGR ACTIVE SON DRG 8 3000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR -40 to 125 I333A
INA333AIDRGT ACTIVE SON DRG 8 250 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR -40 to 125 I333A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
PACKAGE OPTION ADDENDUM
[url]www.ti.com[/url] 12-Aug-2017
Addendum-Page 2
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF INA333 :
NOTE: Qualified Version Definitions:
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
INA333AIDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
INA333AIDGKT VSSOP DGK 8 250 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
INA333AIDRGR SON DRG 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
INA333AIDRGT SON DRG 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
[url]www.ti.com[/url] 7-Apr-2016
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
INA333AIDGKR VSSOP DGK 8 2500 366.0 364.0 50.0
INA333AIDGKT VSSOP DGK 8 250 366.0 364.0 50.0
INA333AIDRGR SON DRG 8 3000 367.0 367.0 35.0
INA333AIDRGT SON DRG 8 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
[url]www.ti.com[/url] 7-Apr-2016
Pack Materials-Page 2





IMPORTANT NOTICE